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1 typical application features description 15v, 5a 2-phase synchronous step-up dc/dc converter with output disconnect the lt c ? 3124 is a dual-phase, synchronous step-up dc/ dc converter with true output disconnect and inrush current limiting capable of providing output voltages up to 15 v. dual-phase operation significantly reduces peak inductor and capacitor ripple currents, minimizing induc - tor and capacitor size. the 2.5 a per phase current limit, along with the ability to program output voltages up to 15v make the ltc3124 well suited for a variety of demanding applications. once started, operation will continue with inputs down to 500mv. the ltc3124 switching frequency can be programmed from 100 khz to 3 mhz to optimize applications for highest efficiency or smallest solution footprint. the oscillator can be synchronized to an external clock for noise sensitive applications. selectable burst mode operation reduces quiescent current to 25 a, ensuring high efficiency across the entire load range. an internal soft-start limits inrush current during start-up. other features include a <1 a shutdown current and robust protection under short - circuit, thermal overload, and output overvoltage conditions. the ltc3124 is offered in both 16-lead dfn and thermally-enhanced tssop packages. 5v to 12v synchronous boost converter efficiency curve applications n v in range: 1.8v to 5.5v, 500mv after start-up n adjustable output voltage: 2.5v to 15v n 1.5a output current for v in = 5v and v out = 12v n dual-phase control reduces output voltage ripple n output disconnects from input when shut down n synchronous rectification: up to 95% efficiency n inrush current limit n up to 3mhz programmable switching frequency synchronizable to external clock n selectable burst mode ? operation: 25a i q n output overvoltage protection n internal soft-start n <1a i q in shutdown n 16-lead, thermally- enhanced 3mm 5mm 0.75mm dfn and tssop packages n rf, microwave power amplifiers n piezo actuators n small dc motors, thermal printers n 12 v analog rail from battery , 5v , or backup capacitor l, lt , lt c , lt m , burst mode, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 100nf v out 12v 1.5a 22f 2 4.7h 4.7h v in 5v swb cap pgndb v outb swa ltc3124 680pf 56pf 3124 ta01a 4.7f 10f 1.02m 113k 84.5k 28k off on v in sgnd pwm/sync sd v cc fb rt v c pgnda v outa burst pwm 100 10 90 70 50 30 80 60 40 20 0 10 1 0.1 0.01 0.001 0.0001 load current (ma) efficiency (%) power loss (w) 3124 ta01b 0.01 1000 100 pwm pwm 10 0.1 1 burst mode operation burst mode operation efficiency power loss f sw = 1mhz ltc3124 3124f for more information www.linear.com/ltc3124
2 absolute maximum ratings v in voltage ................................................... C 0.3 v to 6v v outa , v outb voltages ............................... C 0.3 v to 18 v swa , swb voltages ( note 2) ..................... C 0.3 v to 18 v swa , swb ( pulsed < 100 ns ) ( note 2) ....... C 0.3 v to 19 v vc voltage .................................................. C 0.3 v to v cc rt voltage .................................................. C 0.3 v to v cc cap voltage v out < 5.7 v ............................ C 0.3 v to (v out + 0.3 v) 5.7 v v out 11.7 v...... (v out C 6v) to (v out + 0.3 v) v out > 11.7 v ................................. ( v out C 6v) to 12 v all other pins ............................................... C 0.3 v to 6v operating junction temperature range ( notes 3, 4) ltc 3 124 e/ ltc 3124 i ........................... C 40 c to 125 c ltc 3 124 h .......................................... C4 0 c to 150 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) fe p ackage only ............................................... 30 0 c (note 1) 16 15 14 13 12 11 10 9 17 pgnd 1 2 3 4 5 6 7 8 cap v outb nc v outa sgnd sd fb vc swb pgndb swa pgnda v in pwm/sync v cc rt top view dhc package 16-lead (5mm 3mm) plastic dfn t jmax = 125c, ja = 43c/w (note 5), jc = 5c/w exposed pad (pin 17) is pgnd and must be soldered to pcb for rated thermal performance fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 swb pgndb swa pgnda v in pwm/sync v cc rt cap v outb nc v outa sgnd sd fb vc 17 pgnd t jmax = 150c, ja = 40c/w (note 5), jc = 10c/w exposed pad (pin 17) is pgnd and must be soldered to pcb for rated thermal performance pin configuration order information lead free finish tape and reel part marking* package description temperature range ltc3124edhc#pbf ltc3124edhc#trpbf 3124 16-lead (5mm 3mm) plastic dfn C40c to 125c ltc3124idhc#pbf ltc3124idhc#trpbf 3124 16-lead (5mm 3mm) plastic dfn C40c to 125c ltc3124efe#pbf ltc3124efe#trpbf 3124fe 16-lead plastic tssop C40c to 125c ltc3124ife#pbf ltc3124ife#trpbf 3124fe 16-lead plastic tssop C40c to 125c ltc3124hfe#pbf ltc3124hfe#trpbf 3124fe 16-lead plastic tssop C40c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container .consult lt c marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc3124 3124f for more information www.linear.com/ltc3124
3 electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: voltage transients on the sw pin beyond the dc limit specified in the absolute maximum ratings are non-disruptive to normal operations when using good layout practices, as shown on the demo board or described in the data sheet or application notes. note 3: the ltc3124 is tested under pulsed load conditions such that t a t j . the ltc3124e is guaranteed to meet performance specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3124i is guaranteed to meet specifications over the C40c to 125c operating junction temperature range. the ltc3124h is guaranteed to meet specifications over the full C40c to 150c operating junction range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d in watts) according to the formula: t j = t a + (p d ? ja ) where ja is the thermal impedance of the package. note 4: the ltc3124 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature shutdown is active. continuous operation above the specified maximum operating junction temperature may result in device degradation or failure. note 5: failure to solder the exposed backside of the package to the pc board ground plane will result in a thermal impedance much higher than the rated package specifications. the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 3). v in = 3.6v, v outa = v outb = 12v, r t = 28k unless otherwise noted. parameter conditions min typ max units minimum start-up voltage v out = 0v l 1.6 1.8 v input voltage range v out 2.5v l 0.5 5.5 v output voltage adjust range l 2.5 15 v feedback voltage l 1.176 1.200 1.224 v feedback input current fb = 1.4v 1 50 na quiescent current, shutdown sd = 0v, v out = 0v, not including switch leakage 0.2 1 a quiescent current, active fb = 1.4v, measured on v in , non-switching 600 840 a quiescent current, burst measured on v in , fb = 1.4v measured on v out , fb = 1.4v 25 10 40 20 a a n-channel mosfet switch leakage current sw = 15v, v out = 15v, per phase l 0.1 40 a p-channel mosfet switch leakage current sw = 0v, v out = 15v, sd = 0v, per phase l 0.1 70 a n-channel mosfet switch on-resistance per phase 0.130 p-channel mosfet switch on-resistance per phase 0.200 n-channel mosfet peak current limit per phase l 2.5 3.5 4.5 a maximum duty cycle fb = 1.0v l 90 94 % minimum duty cycle fb = 1.4v l 0 % switching frequency per phase l 0.83 1 1.17 mhz sync frequency range l 0.2 6.0 mhz pwm /sync input high voltage l 0.9 ? v cc v pwm /sync input low voltage l 0.1 ? v cc v pwm /sync input current v pwm /sync = 5.5v 0.01 1 a cap clamp voltage v out > 6.2v, referenced to v out C5.0 C5.4 C5.8 v v cc regulation voltage v in < 2.8v, v out > 5v 3.9 4.25 4.6 v error amplifier transconductance l 60 100 130 s error amplifier sink current fb = 1.6v, vc = 1.15v 25 a error amplifier sour ce current fb = 800mv, vc = 1.15v C25 a soft-start time 10 ms sd input high voltage l 1.6 v sd input low voltage l 0.25 v sd input current sd = 5.5v 1 2 a ltc3124 3124f for more information www.linear.com/ltc3124
4 typical performance characteristics pwm mode operation load transient response inrush current control feedback vs temperature r ds(on) vs temperature, both nmos and pmos switching frequency vs temperature efficiency vs load current, v out = 5v efficiency vs load current, v out = 7.5v efficiency vs load current, v out = 12v 100 10 90 70 50 30 80 60 40 20 0 load current (ma) efficiency (%) 3124 g01 0.01 1000 100 pwm 10 0.1 1 v in = 4.2v v in = 3.3v v in = 0.6v burst mode operation f sw = 1mhz 100 10 90 70 50 30 80 60 40 20 0 load current (ma) efficiency (%) 3124 g02 0.01 1000 100 pwm 10 0.1 1 v in = 5.4v v in = 3.8v v in = 2.3v burst mode operation f sw = 1mhz 100 10 90 70 50 30 80 60 40 20 0 load current (ma) efficiency (%) 3124 g03 0.01 1000 100 pwm 10 0.1 1 v in = 5.4v v in = 4.2v v in = 2.6v burst mode operation f sw = 1mhz temperature (c) ?50 change in r ds(on) from 25c (%) 80 60 40 20 0 ?20 ?40 70 110 ?10 3124 g08 30 150 v out 20mv/div ac-coupled phase a inductor current 500ma/div phase b inductor current 500ma/div 2s/div i load = 500ma 3124 g04 v out 500mv/div ac-coupled output current 500ma/div 500s/div r c = 169k c c = 330pf no c f 3124 g05 150ma 150ma 1500ma sd 5v/div v out 5v/div inductor a current 1a/div inductor b current 1a/div 2ms/div i load = 100ma 3124 g06 temperature (c) ?40 change in v fb from 25c (%) ?0.20 ?0.15 ?0.10 80 160 3124 g07 ?0.25 ?0.30 ?0.35 0 40 120 ?0.05 0 0.05 temperature (c) ?50 ?20 ?2.0 change in frequency from 25c (%) ?1.0 0.5 10 70 100 3124 g09 ?1.5 0 ?0.5 40 130 160 configured as front page application at t a = 25c, unless otherwise specified. ltc3124 3124f for more information www.linear.com/ltc3124
5 typical performance characteristics burst mode output current vs v in burst mode no-load input current vs v in burst mode quiescent current change vs temperature sd pin threshold pwm mode maximum output current vs v in peak current limit change vs temperature pwm operation no-load input current vs v in v in (v) 1 output current (a) 2.4 3.2 4.0 5 3124 g10 1.6 0.8 2.0 2.8 3.6 1.2 0.4 0 2 3 4 1.5 0.5 2.5 3.5 4.5 5.5 v out = 5v v out = 7.5v v out = 12v v out = 15v temperature (c) ?50 peak current limit change from 25c (%) 2 1 0 ?1 ?2 ?3 ?4 70 110 ?10 3124 g11 30 150 v in (v) 1 input current (ma) 120 160 200 5 3124 g12 80 40 100 140 180 60 20 0 2 3 4 1.5 0.5 2.5 3.5 4.5 5.5 v out = 15v v out = 12v v out = 7.5v v out = 5v v out = 2.5v v in , falling (v) 1 output current (ma) 300 400 5 3124 g13 200 100 250 350 150 50 0 2 3 4 1.5 0.5 2.5 3.5 4.5 5.5 v out = 2.5v v out = 5v v out = 7.5v v out = 12v v out = 15v v in , falling (v) 0.5 1 1.5 2 input current (a) 100 1000 10000 2.5 3 3.5 4 4.5 5 5.5 3124 g14 10 v out = 15v v out = 12v v out = 7.5v v out = 5v v out = 2.5v 1s/div 3124 g16 v out 5v/div v sd 500mv/div 900mv 400mv rt vs frequency configured as front page application at t a = 25c, unless otherwise specified. frequency (khz) 100 10 r t resistance (k) 10 100 1000 3000 3124 g17 temperature (c) ?50 change in current from 25c (%) 75 60 45 30 15 0 ?15 70 110 ?10 3124 g15 30 150 ltc3124 3124f for more information www.linear.com/ltc3124
6 typical performance characteristics burst mode operation burst mode operation to pwm mode pwm mode to burst mode operation burst mode transient synchronized operation efficiency vs frequency frequency accuracy cap pin voltage vs v out v cc vs v in v in , falling (v) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 change in frequency (%) 0 1 3124 g19 ?1 ?2 5.5 2 v out = 15v v out = 3.6v v out = 2.5v v out (v) 0 v cap , referred to v out (v) 0 ?3 ?4 ?5 ?2 ?1 ?6 ?7 10 642 3124 g21 8 1412 v in (v) 0 v cc (v) 4.5 4.0 3.5 3.0 2.5 4 21 3124 g22 3 65 v in falling v in rising v out 100mv/div ac-coupled v swa 10v/div phase a inductor current 500ma/div 5s/div output current = 50ma 3124 g23 v out 50mv/div ac-coupled v pwm/sync 2v/div 50s/div output current = 100ma type iii compensation?see figure 10 for component values 3124 g25 v out 100mv/div ac-coupled output current 100ma/div 200s/div 3124 g26 100ma 10ma 10ma v swb 10v/div v swa 10v/div v pwm/sync 5v/div 1s/div output current = 1a 3124 g27 synchronization signal set to 2.6mhz synchronized to 1.3mhz output current (ma) 10 40 efficiency (%) 50 60 70 80 100 1000 3124 g20 30 20 10 0 90 100 100khz efficiency 1mhz efficiency 3mhz efficiency v out 50mv/div ac-coupled v pwm/sync 2v/div 50s/div output current = 100ma type iii compensation?see figure 10 for component values 3124 g24 configured as front page application at t a = 25c, unless otherwise specified. ltc3124 3124f for more information www.linear.com/ltc3124
7 typical performance characteristics output voltage ripple at 1.5 a load with two 10 f ceramic capacitors swa and swb at 1mhz/phase sw pins while synchronizing to 1.2mhz short-circuit response pin functions swb, swa (pin 1, pin 3): phase b and phase a switch pins. connect inductors from these pins to the input sup- ply. keep pcb trace lengths as short and wide as possible to reduce emi and voltage overshoot. when v out v in + 2v, internal anti-ringing resistors are connected between v in and both swa and swb after their respective induc- tor currents have dropped to near zero, to minimize emi. these anti- ringing resistors are also activated in shutdown and during the sleep periods of burst mode operation. pgndb, pgnda, pgnd (pin 2, pin 4, exposed pad pin?17): power ground. when laying out your pcb, provide a short, direct path between pgnd and the output capaci - tors and tie directly to the ground plane. the exposed pad is ground and must be soldered to the pcb ground plane for rated thermal and electrical performance. v in (pin 5): input supply pin. the device is powered from v in if v in is initially greater than approximately 3.5 v, with v in continuing to supply the device down to approximately 3v; otherwise the greater of v in and v out supplies the configured as front page application at t a = 25c, unless otherwise specified. v out 5v/div inductor b current 2a/div inductor a current 2a/div 100s/div i load = 500ma 3124 g28 short-circuit applied short-circuit removed v swa 5v/div v swb 5v/div 500ns/div i load = 1500ma 3124 g29 inductor b current 500ma/div inductor a current 500ma/div v out 20mv/div ac-coupled 500ns/div 3124 g31 v swa 5v/div v swb 5v/div 500ns/div i load = 1500ma 3124 g30 ltc3124 3124f for more information www.linear.com/ltc3124
8 pin functions device. place a low esr ceramic bypass capacitor of at least 10 f from v in to pgnd. x5r and x7r dielectrics are preferred for their superior voltage and temperature characteristics. pwm /sync (pin 6): burst mode operation select and oscillator synchronization. do not leave this pin floating. ? pwm /sync = high. disable burst mode operation and maintain low noise, constant frequency operation. ? pwm /sync = low. the converter operates in burst mode, independent of load current. ? pwm /sync = external clk. the internal oscillator is synchronized to the external clk signal. burst mode operation is disabled. a clock pulse width of 100ns minimum is required to synchronize the oscillator. an external resistor must be connected between r t and sgnd to program the oscillator slightly below the desired synchronization frequency. in non-synchronized applications, repeated clocking of the pwm /sync pin to affect an operating mode change is supported with these restrictions: ? boost mode (v out > v in ): i out < 3 ma: f pwm /sync 10hz, i out 3ma: f pwm /sync 5khz. ? buck mode (v out < v in ): i out < 5 ma: f pwm /sync 2.5hz, i out 5ma: f pwm /sync 5khz. v cc ( pin 7): v cc regulator output. connect a low esr filter capacitor of at least 4.7 f from this pin to sgnd to provide a regulated rail approximately equal to the lower of v in and 4.25 v. when v out is higher than v in , and v in falls below 3 v, v cc will regulate to the lower of approximately v out and 4.25 v. a uvlo event occurs if v cc drops below 1.5v, typical. switching is inhibited, and a soft-start is initiated when v cc returns above 1.6v, typical. rt (pin 8): frequency adjust pin. connect to sgnd through an external resistor (r t ) to program the oscillator frequency according to the formula: f osc ? 56 r t f switch = f osc 2 ? 28 r t where f osc is in mhz and r t is in k. vc (pin 9): error amplifier output. a frequency com- pensation network is connected from this pin to sgnd to compensate the control loop. see compensating the feedback loop section for guidelines. fb (pin 10): feedback input to the error amplifier. con - nect the resistor divider tap to this pin. connect the top of the divider to v out and the bottom of the divider to sgnd. the output voltage can be adjusted from 2.5 v to 15v according to the formula: v out = 1.2v ? 1 + r1 r2 ? ? ? ? ? ? sd ( pin 11): logic controlled shutdown input. pulling this pin above 1.6 v enables normal, free-running operation. forcing this pin below 0.25 v shuts the ltc3124 off, with quiescent current below 1a . do not leave this pin floating. sgnd (pin 12): signal ground. when laying out your pc board, provide a short, direct path between sgnd and the ground referenced sides of all the appropriate components connecting to pins rt , vc, and fb. v outa , v outb (pin 13, pin 15): output voltage senses and the source of the internal synchronous rectifier mosfets . driver bias is derived from v out . connect the output filter capacitor from v out to pgnd, close to the ic. a minimum value of 10 f ceramic per phase is recommended. v out is disconnected from v in when sd is low. v outa and v outb must be tied together. nc ( pin 14): no connect. not connected internally. connect this pin to v outa /v outb to provide a wider v out copper plane on the printed circuit board. cap (pin 16): serves as the low reference for the syn - chronous rectifiers gate drives. connect a low esr filter capacitor (typically 100 nf) from this pin to v out to provide an elevated ground rail, approximately 5.4 v below v out , used to drive the synchronous rectifiers. ltc3124 3124f for more information www.linear.com/ltc3124
9 block diagram ?? + pwm logic and drivers pwm comp current sense i zero comp + ? + ? + + 3.5a swb anti- ring v in en 16.5v ovlo stop switching v outb c cap 100nf cap sd i peak comp adaptive slope comp v out ? 5.4v rail shut down bulk control signals 11 16 nc 14 15 1 swa 3 vc rt r c c c c f 9 8 pgndb pwm/sync 6 v cc exposed pad 3124 bd 7 v in 5 ?? + pwm logic and drivers burst mode control 4.25v ldo soft- start g m error amplifier pwm comp current sense izero comp burst sleep + ? + ? + + 3.5a v in v refup v cc v in tsd v outa i peak comp adaptive slope comp reference 1.2v thermal sd oscillator bulk control signals 13 fb 10 + ? ? + + anti- ring la c in v in 1.8v to 5.5v lb r t r2 r1 2 sgnd 12 pgnda 4 17 c vcc + c out v out 2.5v to 15v sync ltc3124 3124f for more information www.linear.com/ltc3124
10 operation the ltc3124 is a dual- phase, adjustable frequency (100khz to 3 mhz) synchronous boost converter housed in either a 16-lead 5mm 3 mm dfn or a thermally-enhanced tssop package. the ltc3124 offers the unique ability to start up from inputs as low as 1.8 v and continue to operate from inputs as low as 0.5 v, for output voltages greater than 2.5v. the device also features fixed frequency, current mode pwm control for exceptional line and load regula - tion. the current mode architecture with adaptive slope compensation provides excellent load transient response and requires minimal output filtering. an internal 10ms soft-start limits inrush current during start-up and simpli - fies the design process while minimizing the number of external components. with its low r ds( on) and low gate charge internal n- channel mosfet switches and p-channel mosfet synchronous rectifiers, the ltc3124 achieves high efficiency over a wide range of load current. high efficiency is achieved at light loads by utilizing burst mode operation. operation can be best understood by referring to the block diagram. multiphase operation the ltc3124 uses a dual-phase architecture, rather than the conventional single phase of other boost converters. by having two phases equally spaced 180 apart, not only is the output ripple frequency increased by a factor of two, but the output capacitor ripple current is significantly reduced. although this architecture requires two induc - tors, rather than a single inductor, there are a number of important advantages. ? substantially lower peak inductor current allows the use of smaller, lower cost inductors. ? significantly reduced output ripple current minimizes output capacitance requirement. ? higher frequency output ripple is easier to filter for low noise applications. ? input ripple current is also reduced for lower noise on v in . figure 1. comparison of output ripple current with single phase and dual phase boost converter in a 1.5a load application operating at 50% duty cycle the peak inductor current, reduced nearly by a factor of 2 when compared to a single phase step-up converter, is given by: i lpeak ? 1 2 ? i o (1Cd) + ? i l 2 1 where i o is the average load current, d is the pwm duty cycle, and ?i l is the inductor ripple current. this relation- ship is shown graphically in figure 1. with 2- phase operation, one of the phases is always de- livering current to the load whenever v in is greater than one-half v out ( duty cycles less than 50%). as the duty cycle decreases further, load current delivery between the two phases begins to overlap, occurring simultaneously for a growing portion of each phase as the duty cycle ap - proaches zero . this significantly reduces both the output ripple current and the peak current in each inductor, when compared with a single-phase converter. this is illustrated in the waveforms of figures 2 and 3. time (s) 0 output ripple current (a) 3.5 3.0 2.0 1.0 2.5 1.5 0.5 0 1.0 3124 f01 1.5 0.5 single phase dual phase ltc3124 3124f for more information www.linear.com/ltc3124
11 operation figure 2. simplified voltage and current waveforms for 2-phase operation at 50% duty cycle figure 3. simplified voltage and current waveforms for 2-phase operation at 25% duty cycle low voltage operation the ltc3124 is designed to allow start-up from input voltages as low as 1.8 v. when v out exceeds 2.5 v, the ltc3124 continues to regulate its output, even when v in falls as low as 0.5 v. this feature extends operating times by maximizing the amount of energy that can be extracted from the input source. the limiting factors for the applica - tion become the availability of the power source to supply sufficient power to the output at the low input voltage, and the maximum duty cycle, which is clamped at 94%. note that at low input voltages, small voltage drops due to series resistance become critical and greatly limit the power delivery capability of the converter. low noise fixed frequency operation soft-start the ltc3124 contains internal circuitry to provide soft- start operation. the soft- start utilizes a linearly increasing ramp of the error amplifier reference voltage from zero to its nominal value of 1.2 v in approximately 10 ms, with the internal control loop driving v out from zero to its final programmed value. this limits the inrush current drawn from the input source. as a result, the duration of the soft-start is largely unaffected by the size of the output capacitor or the output regulation voltage. the closed-loop nature of the soft-start allows the converter to respond to load transients that might occur during the soft-start interval. the soft-start period is reset by a shutdown command on sd , a uvlo event on v cc (v cc < 1.5v), an overvoltage event on v out (v out 16.5 v), or an overtemperature event ( tsd is invoked when the die temperature exceeds 170c ). upon removal of these fault conditions, the ltc3124 will soft- start the output voltage. error amplifier the noninverting input of the transconductance error amplifier is internally connected to the 1.2 v reference and the inverting input is connected to fb. an external resistive voltage divider from v out to sgnd programs the output voltage from 2.5v to 15v via fb as shown in figure 4. v out = 1.2v 1 + r1 r2 ? ? ? ? ? ? 3124 f02 output ripple current inductor b current inductor a current input current rectifier b current rectifier a current switch b voltage switch a voltage 3124 f03 output ripple current inductor b current inductor a current input current rectifier b current rectifier a current switch b voltage switch a voltage ltc3124 3124f for more information www.linear.com/ltc3124
12 operation thus r t (k) ? 28/f ( mhz). see table 1 for various switch- ing frequencies and their corresponding r t values. table 1. switching frequency and their respective r t switching frequency (khz) r t (k) 100 316 200 154 300 100 500 57.6 800 34.8 1000 28 1200 22.6 2000 13 2200 11.5 3000 8.06 for desired switching frequencies not included in table 1, please refer to the resistance vs frequency curve in the typical performance characteristics section. the oscillator can be synchronized to an external frequency by applying a pulse train of twice the desired switching frequency to the pwm /sync pin. an external resistor must be connected between rt and sgnd to program the oscillator to a frequency approximately 25% below that of the externally applied pulse train used for synchronization. r t is selected in this case according to this formula: r t(sync) (k) 1.25 ? r t(switch) (k) where r t( switch ) is the value of r t at the desired switching frequency, which is half of the synchronization frequency. shutdown the boost converter is disabled by pulling sd below 0.25v and enabled by pulling sd above 1.6 v. note that sd can be driven above v in or v out , as long as it is limited to less than its absolute maximum rating. thermal shutdown if the die temperature exceeds 170 c typical, the ltc3124 will go into thermal shutdown ( tsd). all switches will be shut off until the die temperature drops by approximately 7c, when the device re-initiates a soft-start and switching is re-enabled. ltc3124 r2 1.2v v out 3124 f04 r1 fb + ? figure 4. programming the output voltage selecting an r2 value of 113 k to have approximately 10a of bias current in the v out resistor divider yields the formula: r1 = 94 ? (v out C 1.2v); v out in volts and r1 in k. power converter control loop compensation is set with a simple rc network connected between vc and sgnd. internal current limit current limit comparators shut off the n-channel mosfet switches once their respective peak current is reached. peak switch current per phase is limited to 3.5 a, inde - pendent of input or output voltage, unless v out is below approximately 1.5 v, resulting in the current limit being approximately half of the nominal peak values. lossless current sensing converts the peak current signals of the n- channel mosfet switches into voltages that are summed with their respective internal slope compensation. the summed signals are compared to the error amplifier outputs to provide a peak current control command for the pwms . zero current comparator the zero current comparators monitor the inductor currents being delivered to the output and shut off the synchronous rectifiers when the current is approximately 50 ma. this prevents the inductor currents from reversing in polarity, improving efficiency at light loads. oscillator the internal oscillator is programmed to twice the desired switching frequency with an external resistor from the rt pin to sgnd according to the following formula: f osc (mhz) ? 56 r t (k ? ) ? ? ? ? ? ? = 2 ? f (mhz) where f = switching frequency of one phase. ltc3124 3124f for more information www.linear.com/ltc3124
13 operation boost anti-ringing control when v out v in + 2 v, the anti-ringing circuitry connects a resistor across each inductor to v in to damp high frequency ringing on the sw pins during discontinuous current mode operation. although the ringing of the resonant circuits formed by the inductors and c sw(a/b) ( capacitance on the respective sw pins) is low energy, it can cause emi radiation if not damped. v cc regulator an internal low dropout regulator generates the 4.25v ( nominal) v cc rail from v in or v out , depending upon operating conditions. v cc is supplied from v in if v in is initially greater than approximately 3.5 v , with v in continuing to supply v cc down to approximately 3 v ; otherwise the greater of v in and v out supplies v cc . the v cc rail powers the internal control circuitry and power mosfet gate drivers of the ltc3124. the v cc regulator is disabled in shutdown to reduce quiescent current and is enabled by forcing the sd pin above its input high threshold. a 4.7 f or larger capacitor must be connected between v cc and sgnd. overvoltage lockout an overvoltage condition occurs when v out exceeds approximately 16.5 v. switching is disabled and the in- ternal soft-start ramp is reset. once v out drops below approximately 16 v a soft-start is initiated and switching is allowed to resume. if the boost converter output is lightly loaded such that the time constant of the output capacitance, c out , and the output load resistance, r out is near or greater than the soft- start time of approximately 10ms, the soft-start ramp may end before or soon after switching resumes, defeating the inrush current limiting of the closed-loop soft-start following an overvoltage event. short-circuit protection the ltc3124 output disconnect feature allows output short-circuit protection while maintaining a maximum set current limit. to reduce power dissipation under overload and short-circuit conditions, the peak switch current limits are reduced to approximately 2 a. once v out exceeds approximately 1.5 v, the current limits are reset to their nominal values of 3.5a per phase. output disconnect the ltc3124s output disconnect feature eliminates body diode conduction of the internal p-channel mosfet recti - fiers. this feature allows for v out to discharge to 0 v during shutdown, and draw no current from the input source. inrush current will also be limited at turn-on, minimizing surge currents seen by the input supply. note that to obtain the advantages of output disconnect, there must not be an external schottky diode connected between swa , swb and v out . the output disconnect feature also allows v out to be pulled high, without backfeeding the power source connected to v in . v in > v out operation the ltc3124 step-up converter will maintain voltage regulation even when the input voltage is above the desired output voltage. note that operating in this mode will exhibit lower efficiency and a reduced output current capability. refer to the typical performance characteristics for details. burst mode operation when the pwm /sync pin is held low, the boost converter operates in burst mode, independent of load current. this mode of operation is typically commanded to improve efficiency at light loads and reduce standby current at no load. the output current (i out ) capability in burst mode operation is significantly less than in pwm mode and varies with v in and v out , as shown in figure 5. the logic input thresholds for this pin are determined relative to v cc with a low being less than 10% of v cc and a high being greater than 90% of v cc . the ltc3124 will operate in fixed frequency pwm mode even if burst mode operation is commanded during soft-start. in burst mode operation, only phase a of the ltc3124 is operational, while phase b is disabled. the phase a inductor current is initially charged to approximately 700ma by turning on the n-channel mosfet switch, at which point the n-channel switch is turned off and the p-channel synchronous switch is turned on, delivering current to the output. when the inductor current discharges to approximately zero, the cycle repeats. in burst mode operation, energy is delivered to the output until the nominal ltc3124 3124f for more information www.linear.com/ltc3124
14 operation applications information figure 5. burst mode output current vs v in pcb layout considerations the ltc3124 switches currents as high as 4.5 a at high frequencies. special attention should be paid to the pcb layout to ensure a stable, noise - free and efficient application circuit. figure 6 presents the ltc3124s 4- layer pcb demo board layout ( the schematic of which may be obtained from the quick start guide) to outline some of the primary considerations. a few key guidelines are outlined below: 1. a 4 - layer board is highly recommended for the ltc3124 to ensure stable performance over the full operating voltage and current range. a dedicated/solid ground plane should be placed directly under the v in , v outa , v outb , swa, and swb traces to provide a mirror plane to minimize noise loops from high di/dt and dv/dt edges (see figure 6, 2nd layer). 2. all circulating high current paths should be kept as short as possible. capacitor ground connections should via down to the ground plane in the shortest route possible. the bypass capacitors on v in should be placed as close to the ic as possible and should have the shortest possible paths to ground ( see figure 6, top layer). v in , falling (v) 1 output current (ma) 300 400 5 3124 f05 200 100 250 350 150 50 0 2 3 4 1.5 0.5 2.5 3.5 4.5 5.5 v out = 2.5v v out = 5v v out = 7.5v v out = 12v v out = 15v 3. pgnda pin, pgndb pin, and the exposed pad are the power ground connections for the ltc3124. multiple vias should connect the back pad directly to the ground plane. in addition, maximization of the metallization connected to the back pad will improve the thermal environment and improve the power handling capabili - ties of the ic. 4. the high current components and their connections should all be placed over a complete ground plane to minimize loop cross-sectional areas. this minimizes emi and reduces inductive drops. 5. connections to all of the high current components should be made as wide as possible to reduce the series resistance. this will improve efficiency and maximize the output current capability of the boost converter. 6. to prevent large circulating currents from disrupting the converters output voltage sensing, compensation , and programmed switching frequency, the ground for the resistor divider, compensation components, and rt should be returned to the ground plane using a via placed close to the ic and away from the power connections. regulation value is reached, then the ltc3124 transitions into a very low quiescent current sleep state. in sleep, the output switches are turned off and the ltc3124 consumes only 25 a of quiescent current . when the output volt- age droops approximately 1%, switching resumes. this maximizes efficiency at very light loads by minimizing switching and quiescent losses. output voltage ripple in burst mode operation is typically 1% to 2% peak-to-peak. additional output capacitance (22 f or greater), or the addition of a small feedforward capacitor (10 pf to 50pf) connected between v out and fb can help further reduce the output ripple. ltc3124 3124f for more information www.linear.com/ltc3124
15 applications information 7. keep the connections from the resistor divider to the fb pin and from the compensation components to the vc pin as short as possible and away from the switch pin connections. figure 6. example pcb layout bottom layer ( top view) 3rd layer 2nd layer top layer 8. crossover connections should be made on inner cop- per layers if available. if it is necessary to place these on the ground plane, make the trace on the ground plane as short as possible to minimize the disruption to the ground plane (see figure 6, 3rd layer). ltc3124 3124f for more information www.linear.com/ltc3124
16 applications information schottky diode although it is not required, adding a schottky diode from both sw pins to v out can improve the converter efficiency by up to 4%. note that this defeats the output disconnect and short-circuit protection features of the ltc3124. component selection inductor selection the ltc3124 can utilize small inductors due to its capa - bility of setting a fast (up to 3mhz) switching frequency. larger values of inductance will allow slightly greater output current capability by reducing the inductor ripple current. to design a stable converter the range of induc - tance values is bounded by the targeted magnitude of the internal slope compensation and is inversely proportional to the switching frequency. the inductor selection for the ltc3124 has the following bounds: 10 f h > l > 3 f h the inductor peak-to-peak ripple current is given by the following equation: ripple a ( ) = v in ? v out C v in ( ) f ?l ? v out where: l = inductor v alue in h f = switching frequency in mhz of one phase the inductor ripple current is a maximum at the minimum inductor value. substituting 3/ f for the inductor value in the above equation yields the following: ripple max a ( ) = v in ? v out C v in ( ) 3 ? v out a reasonable operating range for the inductor ripple cur- rent is typically 10% to 40% of the maximum inductor current. high frequency ferrite core inductor materials reduce frequency dependent power losses compared to cheaper powdered iron types, improving efficiency. the inductor should have low dcr ( series resistance of the windings) to reduce the i 2 r power losses, and must be able to support the peak inductor current without saturat- ing. molded chokes and most chip inductors usually do not have enough core area to support the peak inductor currents of 3 a to 4 a seen on the ltc3124. to minimize radiated noise, use a shielded inductor. see table 2 for suggested components and suppliers. table 2. recommended inductors part number value (h) dcr (m ) i s at (a) size ( mm) w l h coilcraft xfl4020-102me 1 12 5.4 4.3 4.3 2.1 coilcraft mss7341t-332nl 3.3 18 3.7 7.3 7.3 4.1 coilcraft xal5030-332me 3.3 23 8.7 5.3 5.3 3.1 coilcraft xal5030-472me 4.7 36 6.7 5.3 5.3 3.1 coilcraft xal5050-562me 5.6 26 6.3 5.3 5.3 5.1 coilcraft xal6060-223me 22 61 5.6 6.3 6.3 6.1 coilcraft mss1260t-333ml 33 57 4.34 12.3 12.3 6.2 coiltronics sd53-1r1-r 1.1 20 4.8 5.2 5.2 3 coiltronics dr74-4r7-r 4.7 25 4.37 7.6 7.6 4.35 coiltronics dr125-330-r 33 51 3.84 12.5 12.5 6 coiltronics dr127-470-r 47 72 5.28 12.5 12.5 8 sumida cdr7d28mnnp-1r2nc 1.2 21 5.9 7.6 7.6 3 sumida cdmc6d28np-3r3mc 3.3 31 5 7.25 6.7 3 taiyo-yuden nr5040t3r3n 3.3 35 3.8 5 5 4 tdk lt f 5022t-1r2n4r2-lc 1.2 25 4.3 5 5.2 2.2 tdk spm6530t-3r3m 3.3 30 6.8 7.1 6.5 3 tdk vlp8040t-4r7m 4.7 25 4.4 8 7.7 4 wrth we-lhmi 74437324010 1 27 9 4.45 4.06 1.8 wrth we-pd 7447789002 2.2 20 4.8 7.3 7.3 3.2 wrth we-pd 7447779002 wrth we -pd 7447789003 2.2 3.3 20 30 6 4.2 7.3 7.3 4.5 7.3 7.3 3.2 wrth we-pd 7447789004 4.7 35 3.9 7.3 7.3 3.2 wrth we-hci 7443251000 10 16 8.5 10 10 5 w rth we-pd 744770122 22 43 5 12 12 8 wrth we-pd 744770133 33 64 3.6 12 12 8 wrth we-pd 7447709470 47 60 4.5 12 12 10 output and input capacitor selection low esr ( equivalent series resistance) capacitors should be used to minimize the output voltage ripple. multilayer ceramic capacitors are an excellent choice as they have extremely low esr and are available in small footprints. x5r and x7r dielectric materials are preferred for their ability to maintain capacitance over wide voltage and tem - perature ranges . y5v types should not be used. although ceramic capacitors are recommended, low esr tantalum capacitors may be used as well. ltc3124 3124f for more information www.linear.com/ltc3124
17 applications information when selecting output capacitors, the magnitude of the peak inductor current, together with the ripple voltage specification, determine the choice of the capacitor. both the esr ( equivalent series resistance) of the capacitor and the charge stored in the capacitor each cycle contribute to the output voltage ripple. the peak- to- peak ripple due to the charge is approximately: v ripple(charge) (v) i p ? v in c out ? v out ? f ? 2 where: i p = peak inductor current f = switching frequency of one phase the esr of c out is usually the most dominant factor for ripple in most power converters. the peak-to-peak ripple due to the capacitor esr is: v ripple(esr) (v) = i load ? r esr ? v out v in where r esr = capacitor equivalent series resistance. the input filter capacitor reduces peak currents drawn from the input source and reduces input switching noise. a low esr bypass capacitor with a minimum value of 10f should be located as close to v in as possible. low esr and high capacitance are critical to maintain low output ripple. capacitors can be used in parallel for even larger capacitance values and lower effective esr. ceramic capacitors are often utilized in switching converter appli - cations due to their small size, low esr and low leakage currents. however, many ceramic capacitors experience significant loss in capacitance from their rated value with increased dc bias voltage. it is not uncommon for a small surface mount capacitor to lose more than 50% of its rated capacitance when operated near its rated voltage. as a result it is sometimes necessary to use a larger capaci - tor value or a capacitor with a larger value and case size, such as 1812 rather than 1206, in order to actually realize the intended capacitance at the full operating voltage. be sure to consult the vendors curve of capacitance versus dc bias voltage. table 3 shows a sampling of capacitors suited for the ltc3124 applications . table 3: representative output capacitors manufacturer, part number v alue (f) voltage (v) size l w h (mm) type, esr (m) avx , 1206yd226 kat 2 a 22 16 3.2 1.6 1.78, x5r ceramic avx , 1210yc226 kat 2 a 22 16 3.2 2.5 2.79, x7r ceramic murata, g rm3 1cr61 c 2 26me15 l 22 16 3.2 1.6 1.8, x5r ceramic murata, g rm32er71 c 22 6k e18 k 22 16 3.2 2.5 2.7, x7r ceramic murata, grm43er61c226ke01l 22 16 4.5 3.2 2.7, x5r ceramic murata , grm32eb31 c 476me15k 47 16 3.2 2.5 2.5, x5r ceramic panasonic , ecj-4yb1c226m 22 16 3.2 2.5 2.7, x5r ceramic taiyo y uden, emk316bj226ml-t 22 16 3.2 1.6 1.8, x5r ceramic t aiyo y uden, emk325b7226mm-tr 22 16 3.2 2.5 2.7, x7r ceramic t aiyo y uden, emk432bj226km-t 22 16 4.5 3.2 2.7, x5r ceramic tdk , c5750x7r1c476m 47 16 5.7 5 2.5, x7r ceramic tdk, c4532x5r0j107m 100 6.3 4.5 3.2 2.8, x5r ceramic nichicon, ubc1c101mns1gs 100 16 8.3 8.3 11.5, aluminum polymer sanyo, 25tqc22mv 22 25 7.3 x 4.3 x 1.9, poscap, 45m sanyo, 16tqc47mw 47 16 7.3 4.3 3.1, poscap, 40m sanyo, 16tqc100m 100 16 7.3 4.3 3.1, poscap, 50m sanyo, 25svpf47m 47 25 6.6 6.6 5.9, os-con, 30m avx , bestcap series bz125a105zlb 1f 5.5 48 30 6.1, 35m, 4 lead cap -xx gs230f 1.2f 4.5 39 17 3.8, 28m tecate powerburst tpl-100/22x45 100 f 2.7 d = 22, h = 45 15m cooper kr-5r5c155-r 1.5f 5.5 d = 21.5, h = 7.5 30m cooper hb1860-2r5117-r 110 f 2.5 d = 18.5, h = 60 20m maxwell bcap0050-p270 50 f 2.5 d = 18, h = 40 20 m ltc3124 3124f for more information www.linear.com/ltc3124
18 applications information for applications requiring a very low profile and very large capacitance, the gs, gs2 and gw series from cap-xx, the bestcap series from avx and powerstor kr series capacitors from cooper all offer very high capacitance and low esr in various low profile packages. operating frequency selection there are several considerations in selecting the operating frequency of the converter. typically, the first consideration is to stay clear of sensitive frequency bands, which can - not tolerate any spectral noise. for example, in products incorporating rf communications, the 455khz if frequency can be sensitive to any noise, therefore switching above 600khz is desired. some communications have sensitivity to 1.1 mhz and in that case a 1.5 mhz switching converter frequency may be employed. a second consideration is the physical size of the converter. as the operating frequency is increased, the inductor and filter capacitors typically can be reduced in value, leading to smaller sized external components. the smaller solution size is typically traded for efficiency, since the switching losses due to gate charge increase with frequency. another consideration is whether the application can allow pulse - skipping. when the boost converter pulse - skips, the minimum on-time of the converter is unable to support the duty cycle. this results in a low frequency component to the output ripple. in many applications where physical size is the main criterion, running the converter in this mode is acceptable. in applications where it is preferred not to enter this mode, the maximum operating frequency is given by: f max _ noskip < ? v out C v in v out ? t on(min) hz where t on(min) = minimum on-time, which is typically around 100ns. thermal considerations for the ltc3124 to deliver its full power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package. this can be accom - plished by taking advantage of the large thermal pad on the underside of the ic. it is recommended that multiple vias in the printed circuit board be used to conduct heat away from the ic and into a copper plane with as much area as possible. if the junction temperature rises above ~170c, the part will trip an internal thermal shutdown, and all switching will stop until the junction temperature drops ~7c. compensating the feedback loop the ltc3124 uses current mode control, with internal adaptive slope compensation. current mode control elimi - nates the second order filter due to the inductor and output capacitor exhibited in voltage mode control, and simplifies the power loop to a single pole filter response. because of this fast current control loop, the power stage of the ic combined with the external inductor can be modeled by a transconductance amplifier g mp and a current controlled current source. figure 7 shows the key equivalent small signal elements of a boost converter. the dc small-signal loop gain of the system shown in figure 7 is given by the following equation: g boost = g ea ?g mp ?g power ? r2 r1 + r2 where g ea is the dc gain of the error amplifier, g mp is the modulator gain, and g power is the inductor current to v out gain. g ea = g ma ? r o 1000v/v (not adjustable; g ma 100s, r o 10m) g mp = 2 ? g mp ; g mp = ? i l ? v c 3.4s not adjustable ( ) g power = ? v out ? i l = ? v in 2 ?i out = ? v in ?r l 2 ? v out ltc3124 3124f for more information www.linear.com/ltc3124
19 applications information phase lead zero: z4 = 1 2 ? r1 + r pl ( ) ?c pl hz phase lead pole: p4 = 1 2 ? r1?r2 r1 + r2 + r pl ? ? ? ? ? ? ?c pl hz error amplifier filter pole: p5 = 1 2 ?r c ? c c ?c f c c + c f hz, c f < c c 10 1 2 ?r c ?c f hz the current mode zero ( z3) is a right-half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. also note that the rhp zero is a minimum at minimum input voltage and maximum output current for a given output voltage. as a general rule, the frequency at which the open-loop gain of the converter is reduced to unity, known as the crossover frequency f c , should be set to less than one-sixth of the right-half plane zero ( z3), and under one- eighth of the switching frequency f switch . once f c is selected, the compensation component values can be calculated using a bode plot of the power stage or two generally valid assumptions: p1 dominates the gain of the power stage for frequencies lower than f c and f c is much higher than p2. first calculate the power stage gain at f c , g fc in v/v. assuming the output pole p1 dominates g fc for this range, it is expressed by: g fc g dc 1 + f c p1 ? ? ? ? ? ? 2 v/v r2 1.2v reference v out 3124 f07 r1 r pl i l c pl r o c c : compensation capacitor r c : compensation resistor c f : high frequency filter capacitor c pl : phase lead capacitor r pl : phase lead resistor g ma : transconductance amplifier inside ic r o : output resistance of g ma g mp : power stage transconductance amplifier c out : output capacitor r esr : output capacitor esr r l : output resistance defined as v out /i load(max) r1, r2: feedback resistor divider network : conversion efficiency (~90% at higher currents) r c c c c f r l fb error amplifier modulator vc r esr c out + ? g mp + ? i l v in 2 v out g ma figure 7. boost converter equivalent model combining the two equations above yields: g dc = g mp ?g power 3.4 ? ? v in ?r l v out v/v converter efficiency will vary with i out and switching frequency f switch as shown in the typical performance characteristics curves. output pole: p1 = 2 2 ?r l ?c out hz error amplifier pole: p2 = 1 2 ?r o ? c c + c f ( ) hz; c f < c c 10 1 2 ?r o ?c c hz; extremelyclose todc error amplifier zero: z1 = 1 2 ?r c ?c c hz esr zero: z2 = 1 2 ?r esr ?c out hz rhp zero: z3 = v in 2 ? 2r l 2 ? v out 2 ?l hz high frequency pole: p3 > f osc 3 hz ltc3124 3124f for more information www.linear.com/ltc3124
20 applications information decide how much phase margin ( m ) is desired. greater phase margin can offer more stability while lower phase mar - gin can yield faster transient response. typically, m 60 is optimal for minimizing transient response time while allowing sufficient margin to account for component variability. 1 is the phase boost of z1, p2, and p5 while 2 is the phase boost of z4 and p4. select 1 and 2 such that: 1 + 2 = m + tan ? 1 ? c z3 ? ? ? ? ? ? and 1 74 ; 2 2 ? tan ? 1 v out 1.2v ? ? ? ? ? ? ? 90 where v out is in v and ? c and z3 are in khz. setting z1, p5, z4, and p4 such that z1 = ? c a 1 , p5 = ? c a 1 , z4 = ? c a 2 , p4 = ? c a 2 allows a 1 and a 2 to be determined using 1 and 2 a 1 = tan 2 1 + 90 2 ? ? ? ? ? ? , a 2 = tan 2 2 + 90 2 ? ? ? ? ? ? the compensation will force the converter gain g boost to unity at ? c by using the following expression for c c : c c = 10 3 ? g ma ? r2 ? g ?c a 1 ? 1 ( ) a 2 2 ? ? c ? r1 + r2 ( ) a 1 pf (g ma in s, ? c in khz, g ?c in v/v) once c c is calculated, r c and c f are determined by: r c = 10 6 ? a 1 2 ? ? c ? c c k ? (? c in khz, c c in pf) c f = c c a 1 ? 1 a method for improving the converter s transient response uses a small feedforward series network of a capacitor and a resistor across the top resistor of the feedback divider (from v out to fb). this adds a phase-lead zero and pole to the transfer function of the converter. the values of these phase lead components are given by the expressions: r pl = r1 ? a 2 ? r1? r2 r1 + r2 ? ? ? ? ? ? a 2 ? 1 k ? and c pl = 10 6 a 2 ? 1 ( ) r1 + r2 ( ) 2 ? ? c ? r1 2 a 2 pf where r1, r2, and r pl are in k and ? c is in khz. note that selecting 2 = 0 forces a 2 = 1, and so the converter will have type ii compensation and therefore no feedforward: r pl is open ( infinite impedance) and c pl = 0 pf. if a 2 = 0.833 ? v out ( its maximum), feedforward is maximized; r pl = 0 and c pl is maximized for this com- pensation method. once the compensation values have been calculated, ob- taining a converter bode plot is strongly recommended to verify calculations and adjust values as required. using the circuit in figure 8 as an example, table 4 shows the parameters used to generate the bode plot shown in figure 9. table 4. bode plot parameters parameter value units comment v in 5 v app specific v out 12 v app specific r l 8 app specific c out at no bias c out at 12v bias 22 2 14 2 f f app specific app specific r esr 2.5 m app specific la, lb 4.7 h app specific f switch 1 mhz adjustable r1 1020 k adjustable r2 113 k adjustable g ma 100 s fixed r o 10 m fixed g mp 3.4 s fixed 90 % app specific r c 84.5 k adjustable c c 680 pf adjustable c f 56 pf adjustable r pl open k optional c pl 0 pf optional ltc3124 3124f for more information www.linear.com/ltc3124
21 applications information switching waveforms with 1.5a load transient response with 700ma to 1.5a load step figure 8. 1mhz, 5v to 12v, 1.5a boost converter figure 9. bode plot for example converter c1 100nf v out 12v 1.5a lb 4.7h la 4.7h v in 5v swb cap pgndb v outb swa ltc3124 c out 22f 2 c c 680pf c f 56pf 3124 f08 c vcc 4.7f c in 10f r1 1.02m r2 113k r c 84.5k r t 28k c1: 100nf, 16v, x5r, 0805 c in : 10f, 10v, x5r, 1206 c out : 22f 2, 16v, x5r, 1210 c vcc : 4.7f, 10v, x5r, 1206 la, lb: coilcraft xal5030-472me off on v in sgnd pwm/sync sd v cc fb rt v c pgnda v outa burst pwm v out 20mv/div ac-coupled v swb 10v/div v swa 10v/div 200ns/div 3124 f08b inductor b current 1a/div inductor a current 1a/div v out 500mv/div ac-coupled output current 500ma/div 100s/div 3124 f08c 700ma 700ma 1500ma frequency (hz) 100 1k ?15 gain (db) phase (deg) 0 15 10k 100k 3124 f09 ?30 ?45 30 45 ?90 ?45 0 45 ?135 ?180 90 phase gain ltc3124 3124f for more information www.linear.com/ltc3124
22 applications information figure 11. bode plot showing phase lead figure 10. boost converter with phase lead c1 100nf c pl 12pf v out 12v 1.5a lb 4.7h la 4.7h v in 5v swb cap pgndb v outb swa ltc3124 c out 22f 2 c c 470pf c f 120pf 3124 f10 c vcc 4.7f c in 10f r1 1.02m r pl 787k r2 113k r c 71.5k r t 28k c1: 100nf, 16v, x5r, 0805 c in : 10f, 10v, x5r, 1206 c out : 22f 2, 16v, x5r, 1210 c vcc : 4.7f, 10v, x5r, 1206 la, lb: coilcraft xal5030-472me off on v in sgnd pwm/sync sd v cc fb rt v c pgnda v outa burst pwm table 5. bode plot parameters parameter value units comment v in 5 v app specific v out 12 v app specific r l 8 app specific c out at no bias c out at 12v bias 22 2 14 2 f f app specific app specific r esr 2.5 m app specific la, lb 4.7 h app specific f switch 1 mhz adjustable r1 113 k adjustable r2 1020 k adjustable g ma 100 s fixed r o 10 m fixed g mp 3.4 s fixed 90 % app specific r c 71.5 k adjustable c c 470 pf adjustable c f 120 pf adjustable r pl 787 k adjustable c pl 12 pf adjustable from figure 9, the phase is ~60 when the gain reaches 0db, so the phase margin of the converter is ~60. the crossover frequency is ~10 khz, which is more than six times lower than the 94 khz frequency of the rhp zero to achieve adequate phase margin. the circuit in figure 10 shows the same application as that in figure 8 with type iii compensation. this is ac- complished by adding c pl and r pl and adjusting c c , c f , and r c accordingly. table 5 shows the parameters used to generate the bode plot shown in figure 11. from figure 11, the phase margin is still optimized at ~60 and the crossover frequency remains ~10 khz. adding cpl and rpl provides some feedforward signal in burst mode operation, leading to lower output voltage ripple. frequency (hz) 100 1k ?15 gain (db) phase (deg) 0 15 10k 100k 3124 f11 ?30 ?45 30 45 ?90 ?45 0 45 ?135 ?180 90 phase gain ltc3124 3124f for more information www.linear.com/ltc3124
23 typical applications 2-port usb-powered 1 mhz synchronous boost converter to 5v, 500ma c1 100nf v out 5v 500ma c out 100f 2 lb 3.3h la 3.3h v in 4.3v to 5.5v swb cap pgndb v outb swa ltc3124 c c 2.7nf c f 270pf 3124 ta03a c vcc 4.7f c in 10f c2 10f r1 1.47m r2 464k r c 35.7k r t 28k c1: 100nf, 16v, x5r, 0805 c2: kemet t491c106k025as c in : 10f, 10v, x5r, 1206 c out : 100f 2, 6.3v, x5r, 1812 c vcc : 4.7f, 10v, x5r, 1206 la, lb: coilcraft xal5030-332me off on v in sgnd pwm/sync sd v cc fb rt v c pgnda v outa single li cell to 6v, 9w, 2.2mhz synchronous boost converter for rf transmitter load step bode plot c1 100nf v out 6v 1.5a c out 47f 2 lb 2.2h la 2.2h v in 2.7v to 4.2v swb cap pgndb v outb swa ltc3124 c c 1.2nf c f 68pf 3124 ta02a c vcc 4.7f c in 10f r1 1.13m r2 280k r c 60.4k r t 11.5k c1: 100nf, 16v, x5r, 0805 c in : 10f, 10v, x5r, 1206 c out : 47f 2, 16v, x5r, 1210 c vcc : 4.7f, 10v, x5r, 1206 la, lb: wrth we-pd 7447779002 off on v in sgnd pwm/sync sd v cc fb rt v c pgnda v outa v out 500mv/div ac-coupled output current 500ma/div 100s/div v in = 3.6v 3124 ta02b 150ma 150ma 1.5a frequency (hz) ?20 gain (db) phase (deg) 40 50 ?30 ?40 30 0 20 10 ?10 100 10k 100k 3124 ta02c ?50 ?90 90 120 ?120 ?150 60 ?30 30 0 ?60 ?180 1k phase gain v in 2v/div v out 2v/div input current 500ma/div 2ms/div r load = 10 v in = usb 2.0 2-port hot plugged 3124 ta03b 2-port usb 2.0 hot plugged ltc3124 3124f for more information www.linear.com/ltc3124
24 typical applications single li cell to 5v, 1.8a synchronized 1.2mhz switching boost converter for rfpa power supply c1 100nf v out 5v 1.8a c out 22f 2 lb 3.3h la 3.3h v in 2.7v to 4.2v swb cap pgndb v outb swa ltc3124 c c 1.5nf c f 150pf 3124 ta05a c vcc 4.7f c in 10f 2.4mhz sync pulse r1 1.47m r2 464k r c 31.6k r t 28.7k c1: 100nf, 16v, x7r, 0805 c in : 10f, 10v, x7r, 1206 c out : 22f 2, 16v, x7r, 1210 c vcc : 4.7f, 10v, x7r, 1206 la, lb: coilcraft mss7341t-332nl off on v in sgnd pwm/sync sd v cc fb rt v c pgnda v outa efficiency 3.3v to 12v, 300khz synchronous boost converter with output disconnect, 1a c1 100nf v out 12v 1a c out 47f 3 lb 22h la 22h v in 3.3v swb cap pgndb v outb swa ltc3124 c c 3.9nf c f 270pf 3124 ta04a c vcc 4.7f c in 10f r1 1.02m r2 113k r c 76.8k r t 100k c1: 100nf, 16v, x5r, 0805 c in : 10f, 10v, x5r, 1206 c out : 47f 3, 16v, x5r, 1210 c vcc : 4.7f, 10v, x5r, 1206 la, lb: wrth we-pdf 7447998221 burst pwm v in sgnd pwm/sync sd v cc fb rt v c pgnda v outa off on efficiency load current (ma) 0.01 0.1 40 efficiency (%) 50 60 70 80 1 10 100 1000 3124 ta04b 30 20 10 0 90 100 pwm burst mode operation v cc derived from v in v cc derived from v out load current (ma) 0.01 0.1 40 efficiency (%) 50 60 70 80 1 10 100 1000 3124 ta05b 30 20 10 0 90 100 pwm burst mode operation 4.2v in 3.3v in 2.7v in ltc3124 3124f for more information www.linear.com/ltc3124
25 typical applications 1.8v to 5.5v input to 15v output, 500khz synchronous boost converter with output disconnect, 300ma single li cell to 12v, 1mhz synchronous boost converter with output disconnect, 800ma c1 100nf v out 15v 300ma c out 22f 2 lb 10h la 10h v in 1.8v to 5.5v swb cap pgndb v outb swa ltc3124 c c 3.3nf c f 100pf 3124 ta06a c vcc 4.7f c in 10f r1 1.3m r2 113k r c 49.9k r t 57.6k c1: 100nf, 16v, x7r, 0805 c in : 10f, 10v, x7r, 1206 c out : 22f 2, 16v, x7r, 1210 c vcc : 4.7f, 10v, x7r, 1206 la, lb: wrth we-hci 7443251000 off on v in sgnd pwm/sync sd v cc fb rt v c pgnda v outa efficiency v in (v) 1.5 efficiency (%) 90 95 100 3 4 5.5 3124 ta06b 85 80 75 2 2.5 3.5 4.5 5 output current = 300ma c1 100nf v out 12v 800ma c out 22f 2 lb 5.6h la 5.6h v in 2.7v to 4.2v swb cap pgndb v outb swa ltc3124 c c 680pf c f 47pf 3124 ta08 c vcc 4.7f c in 10f r1 1.02m r2 113k r c 88.7k r t 28k c1: 100nf, 16v, x7r, 0805 c in : 10f, 10v, x7r, 1206 c out : 22f 2, 16v, x7r, 1210 c vcc : 4.7f, 10v, x7r, 1206 la, lb: coilcraft xal5050-562me off on v in sgnd pwm/sync sd v cc fb rt v c pgnda v outa ltc3124 3124f for more information www.linear.com/ltc3124
26 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05 dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706 rev ?) ltc3124 3124f for more information www.linear.com/ltc3124
27 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. fe16 (bc) tssop rev j 1012 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 10 detail b is the part of the lead frame feature for reference only no measurement purpose 9 4.90 ? 5.10* (.193 ? .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 2.94 (.116) 0.48 (.019) ref 0.51 (.020) ref 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev j) exposed pad variation bc detail b ltc3124 3124f for more information www.linear.com/ltc3124
28 ? linear technology corporation 2014 lt 0614 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3124 related parts typical application dual supercapacitor backup power supply, 0.5v to 5.4v pwm rundown curve burst mode rundown curve c1 100nf v out 5v v in c out 100f 2 lb 3.3h la 3.3h v in 0.5v to 5.4v swb cap pgndb v outb swa ltc3124 c c 1.5nf c f 47pf 3124 ta07a c vcc 4.7f sc1 100f sc2 100f r1 1.47m r2 464k r c 59k r3 1m r t 28k c1: 100nf, 16v, x5r, 0805 c in : 10f, 10v, x5r, 1206 c out : 100f 2, 6.3v, x5r, 1812 c vcc : 4.7f, 10v, x5r, 1206 la, lb: coilcraft xal5030-332me sc1, sc2: tecate powerburst tpl-100/22x45 c in 10f v in sgnd pwm/sync sd fb v cc rt v c pgnda v outa + + off on part number description comments ltc3459 70ma i sw , 10v micropower synchronous boost converter with output disconnect, burst mode operation v in : 1.5v to 5.5v, v out(max) = 10v, i q = 10a, i sd < 1a, thinsot package ltc 3528 1a i sw , 1mhz, synchronous step-up dc/dc converter with output disconnect, burst mode operation 94% efficiency v in : 700mv to 5.25v, v out(max) = 5.25v, i q = 12a, i sd < 1a, 2mm 3mm dfn package ltc3539 2a i sw , 1mhz/2mhz, synchronous step-up dc/dc converters with output disconnect, burst mode operation 94% efficiency v in : 700mv to 5.25v, v out(max) = 5.25v, i q = 10ua, i sd < 1a, 2mm 3mm dfn package ltc3421 3a i sw , 3mhz, synchronous step-up dc/dc converter with output disconnect 95% efficiency v in : 0.5v to 4.5v, v out(max) = 5.25v, i q = 12a, i sd < 1a, qfn24 package ltc3428 4a i sw , 2mhz (1mhz switching), dual phase step-up dc/dc converter 92% efficiency v in : 1.6v to 4.5v, v out(max) = 5.25v, i sd < 1a, 3mm 3mm dfn package ltc3425 5a i sw , 8mhz, low ripple, 4-phase synchronous step-up dc/dc converter with output disconnect 95% efficiency v in : 0.5v to 4.5v, v out(max) = 5.25v, i q = 12a, i sd < 1a, qfn32 ltc3122 2.5a i sw , 3mhz, synchronous step-up dc/dc converter with output disconnect, burst mode operation 95% efficiency v in : 1.8v to 5.5v [500mv after start-up], v out(max) = 15v, i q = 25a, i sd < 1a, 3mm 4mm dfn and msop packages ltc 3112 15v, 2.5a, 750khz, synchronous buck-boost dc/dc converter with output disconnect, burst mode operation 95% efficiency v in : 2.7v to 15v, v out(max) = 14v, i q = 50a, i sd < 1a, 4mm 5mm dfn and tssop packages ltc3114-1 40v, 1a, 2mhz, synchronous buck-boost dc/dc converter with output disconnect, output current limit, burst mode operation 95% efficiency v in : 2.2v to 40v, v out(max) = 40v, i q = 30a, i sd = 3a, 3mm 5mm dfn and tssop packages ltc3115-1 40v, 2a, 2mhz, synchronous buck-boost dc/dc converter with output disconnect, burst mode operation 95% efficiency v in : 2.7v to 40v, v out(max) = 40v, i q = 30a, i sd = 3a, 4mm 5mm dfn and tssop packages v in 2v/div v out 5v/div output current 100ma/div sd 2v/div 200s/div 3124 ta07b supply removed from supercap v in 2v/div v out 5v/div output current 20ma/div sd 2v/div 500s/div 3124 ta07c supply removed from supercap ltc3124 3124f for more information www.linear.com/ltc3124

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